Traditional fabrication processes used in the manufacture of semiconductor devices employ microlithography to pattern integrated circuits onto a circular wafer formed of a semiconductor such as silicon or the like. Typically, the patterned wafers are segmented into individual integrated circuit chips or dies to separate the integrated circuits from one another. The individual integrated circuit chips are assembled or packaged using a variety of packaging technologies to form semiconductor devices that may be mounted to a printed circuit board.
Over the years, packaging technologies have evolved to develop smaller, cheaper, more reliable and more environmentally-friendly packages. For example, chip-scale packaging technologies have been developed that employ direct surface mountable packages having a surface area that is no greater than 1.2 times the area of the integrated circuit chip. Wafer level packaging is an emerging chip-scale packaging technology that encompasses a variety of techniques whereby integrated circuit chips are packaged at wafer level, prior to singulation. Wafer level packaging extends the wafer fabrication processes to include device interconnection and device protection processes. Consequently, wafer level packaging streamlines the manufacturing process by allowing for the integration of wafer fabrication, packaging, testing, and burn-in processes at the wafer level.